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MC74HC73A Dual J-K Flip-Flop with Reset
High-Performance Silicon-Gate CMOS
The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip-flop is negative-edge clocked and has an active-low asynchronous reset. The MC74HC73A is identical in function to the HC107, but has a different pinout.
Features
14 1
http://onsemi.com MARKING DIAGRAMS
14 PDIP-14 N SUFFIX CASE 646 1 14 14 1 SOIC-14 D SUFFIX CASE 751A 1 14 14 1 TSSOP-14 DT SUFFIX CASE 948G 1 HC 73A ALYWG G HC73AG AWLYWW MC74HC73AN AWLYYWWG
* * * * * * * *
Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the JEDEC Standard No. 7.0 A Requirements Chip Complexity: 92 FETs or 23 Equivalent Gates These are Pb-Free Devices
LOGIC DIAGRAM
J1 CLOCK 1 K1 RESET 1 J2 CLOCK 2 K2 RESET 2 14 1 3 2 7 5 10 6 PIN 4 = VCC PIN 11 = GND 8 Q2 13 Q1 12 Q1
PIN ASSIGNMENT
CLOCK 1 RESET 1 K1 VCC CLOCK 2 9 RESET 2 Q2 J2 1 2 3 4 5 6 7 14 13 12 11 10 9 8
J1
Q1 Q1 GND K2 Q2 Q2
A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
FUNCTION TABLE
Inputs Reset L H H H H H H H Clock X J X L L H H X X X K X L H L H X X X Outputs Q Q L H No Change L H H L Toggle No Change No Change No Change
L H
(c) Semiconductor Components Industries, LLC, 2009
December, 2009 - Rev. 7
1
Publication Order Number: MC74HC73/D
MC74HC73A
MAXIMUM RATINGS*
Symbol VCC Vin Vout Iin Iout ICC PD Tstg TL Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Plastic DIP SOIC Package Value - 0.5 to + 7.0 - 1.5 to VCC + 1.5 - 0.5 to VCC + 0.5 20 25 50 750 500 - 65 to + 150 260 Unit V V V mA mA mA mW _C _C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin, Vout TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min 2.0 0 - 55 0 0 0 Max 6.0 VCC + 125 1000 500 400 Unit V V _C ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Test Conditions Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 A Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 A Vin = VIH or VIL |Iout| v 20 A Vin = VIH or VIL VOL Maximum Low-Level Output Voltage Vin = VIH or VIL |Iout| v 20 A Vin = VIH or VIL Iin ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Vin = VCC or GND Iout = 0 A |Iout| v 4.0 mA |Iout| v 5.2 mA |Iout| v 4.0 mA |Iout| v 5.2 mA VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 - 55 to 25_C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 4 v 85_C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 40 v 125_C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9 3.70 5.20 0.1 0.1 0.1 0.40 0.40 1.0 80 A A V Unit V
VIL
V
VOH
V
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MC74HC73A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit Symbol fmax Parameter Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Maximum Propagation Delay, Clock to Q or Q (Figures 1 and 4) Maximum Propagation Delay, Reset to Q or Q (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Input Capacitance VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- - 55 to 25_C 6.0 30 35 125 25 21 155 31 26 75 15 13 10 v 85_C 4.8 24 28 155 31 26 195 39 33 95 19 16 10 v 125_C 4.0 20 24 190 38 32 235 47 40 110 22 19 10 Unit MHz
tPLH, tPHL tPLH, tPHL tTLH, tTHL Cin
ns
ns
ns
pF
Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Flip-Flop)* 35 pF * Used to determine the no-load dynamic power consumption: P D = CPD VCC 2 f + ICC VCC .
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit Symbol tsu Parameter Minimum Setup Time, J or K to Clock (Figure 3) Minimum Hold Time, Clock to J or K (Figure 3) Minimum Recovery Time, Reset Inactive to Clock (Figure 2) Minimum Pulse Width, Clock (Figure 1) Minimum Pulse Width, Reset (Figure 2) Maximum Input Rise and Fall Times (Figure 1) VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - 55 to 25_C 100 20 17 3 3 3 100 20 17 80 16 14 80 16 14 1000 500 400 v 85_C 125 25 21 3 3 3 125 25 21 100 20 17 100 20 17 1000 500 400 v 125_C 150 30 26 3 3 3 150 30 26 120 24 20 120 24 20 1000 500 400 Unit ns
th
ns
trec
ns
tw
ns
tw
ns
tr, tf
ns
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MC74HC73A
SWITCHING WAVEFORMS
CLOCK
tf 90% 50% 10% tw
tr
VCC RESET GND
tw VCC 50% GND tPHL
1/fmax tPLH tPHL Q or Q 90% 50% 10%
Q
50% tPLH
Q tTLH tTHL CLOCK
50% trec VCC 50% GND
Figure 1.
Figure 2.
VALID VCC J or K GND tsu CLOCK 50% GND th VCC DEVICE UNDER TEST OUTPUT TEST POINT
CL*
Figure 3.
*Includes all probe and jig capacitance
Figure 4.
EXPANDED LOGIC DIAGRAM
RESET 2, 6 12, 9
CL J 14, 7 CL
Q
K
3, 10 CL CL
CL CL
CL
CL CL
CL
CL
CLOCK
1, 5 CL CL 13, 8 Q
CL
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MC74HC73A
ORDERING INFORMATION
Device MC74HC73ANG MC74HC73ADG MC74HC73ADR2G MC74HC73ADTR2G Package PDIP-14 (Pb-Free) SOIC-14 (Pb-Free) SOIC-14 (Pb-Free) TSSOP-14* Shipping 25 Units / Rail 55 Units / Rail
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74HC73A
PACKAGE DIMENSIONS
PDIP-14 CASE 646-06 ISSUE P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10 _ 0.38 1.01
14
8
B
1 7
A F N -T-
SEATING PLANE
L C
H
G
D 14 PL
K
M
J M
DIM A B C D F G H J K L M N
0.13 (0.005)
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MC74HC73A
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE H
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
G C -T-
SEATING PLANE
R X 45 _
F
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04 1 0.58
14X
14X
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74HC73A
PACKAGE DIMENSIONS
TSSOP-14 CASE 948G-01 ISSUE B
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K K1 J J1
0.15 (0.006) T U
S
A -V-
SECTION N-N
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 -W- K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_
SOLDERING FOOTPRINT*
7.06 1
0.36
14X
14X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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EEE CCC EEE CCC
0.65 PITCH
DIMENSIONS: MILLIMETERS
MC74HC73A
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC74HC73/D

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